Semiconductor manufacturers typically test integrated circuits to weed out defective integrated circuits after fabrication. It is typical in the art to divide the whole device under test into plural sets of scan chains consisting of flip-flops storing various states of the device. These flip-flops generally correspond to state storing portions of the device. Each scan chain has an input, a serial set of flip-flops holding a subset of the states of the device under test and an output. Such serial scan chains permit testing of the circuit under test as follows. Data is loaded into the registers of the circuit under test via the serial scan chains in a test mode. In the test mode each scan chain provides a serial path between an input, some of the data registers of the circuit under test and an output. This sets the conditions of the circuit under test into a desired state by scanning in appropriate data. The set of parallel scan chains are generally designed to include registers storing data relevant to the internal condition of the circuit under test. After loading the data in this manner, the circuit under test operates in a normal mode responsive to its own clock signal for an interval. This operational interval results in a changed state of the device under test reflected in an altered set of states in the flip-flops of the scan chains. The altered internal state of the circuit under test is output via the same scan chains. This view of the internal state of the circuit under test is compared with an expected state. It is typical to scan in a new initial state for a next test while scanning out data from a prior test.
Integrated circuit test typically uses data compression to transfer data into and out of the tested integrated circuit. This is often called scan based test. Typical designs include many tens or hundreds of separate scan chains. The number of inputs and outputs available for test is typically much smaller and may be less than ten. It is known in the art to employ test data compression for this problem. The test pattern supplied to the integrated circuit is compressed before supply. A decompressor in the integrated circuit receives the compressed data and generates decompressed test data for application to the plural serial scan chains. A compactor typically receives the scan out data from the plural serial scan chains and compacts this data for output via the few output lines.
There are some disadvantages to this scanned based test technique. When scanning in data during initialization and scanning out data following a test, generally more flip-flops will toggle than during any operational mode of the integrated circuit. This has adverse implications for the power consumption of the device. Scanning a device under test may consume much more power than the designed operating power. This may adversely impact the thermal design of the integrated circuit. This thermal problem may be mitigated by scanning at a clock frequency much smaller than the operating frequency. This technique may reduce the average power consumption to within the thermal design of the operating device. At that same time a reduced scanning rate would increase scan-in and scan-out times and consequently the test time. This technique would not reduce the peak power which is dependent upon the number of flip-flops switching simultaneously. Switching a large number of flip-flops simultaneously may cause improper operation of the scan chain due to large IR voltage drops.